### Eclipse Workspace Patch 1.0
#P ChibiOS (SF trunk)
Index: os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
===================================================================
--- os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h	(revision 15973)
+++ os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h	(working copy)
@@ -56,6 +56,35 @@
 #endif
 
 /**
+ * @brief   DAC1 mode control.
+ */
+#if !defined(STM32_DAC_DAC1_MCR) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC1_MCR                  0U
+#endif
+
+
+/**
+ * @brief   DAC2 mode control.
+ */
+#if !defined(STM32_DAC_DAC2_MCR) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC2_MCR                  0U
+#endif
+
+/**
+ * @brief   DAC3 mode control.
+ */
+#if !defined(STM32_DAC_DAC3_MCR) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC3_MCR                  0U
+#endif
+
+/**
+ * @brief   DAC4 mode control.
+ */
+#if !defined(STM32_DAC_DAC4_MCR) || defined(__DOXYGEN__)
+#define STM32_DAC_DAC4_MCR                  0U
+#endif
+
+/**
  * @brief   DAC1 CH1 driver enable switch.
  * @details If set to @p TRUE the support for DAC1 channel 1 is included.
  * @note    The default is @p FALSE.
@@ -487,7 +516,7 @@
 /**
  * @brief   Max DAC channels.
  */
-#if STM32_DAC_DUAL_MODE == FALSE
+#if STM32_DAC_DUAL_MODE == TRUE
 #define DAC_MAX_CHANNELS                    2
 #else
 #define DAC_MAX_CHANNELS                    1
Index: os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
===================================================================
--- os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c	(revision 15973)
+++ os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c	(working copy)
@@ -67,7 +67,8 @@
   STM32_DMA_GETCHANNEL(STM32_DAC_DAC4_CH2_DMA_STREAM,                       \
                        STM32_DAC4_CH2_DMA_CHN)
 
-#define CHANNEL_DATA_OFFSET 3U
+#define CHANNEL_DATA_OFFSET     3U
+#define CHANNEL_REGISTER_SHIFT  16U
 
 /*===========================================================================*/
 /* Driver exported variables.                                                */
@@ -140,7 +141,7 @@
 static const dacparams_t dac1_ch2_params = {
   .dac          = DAC1,
   .dataoffset   = CHANNEL_DATA_OFFSET,
-  .regshift     = 16U,
+  .regshift     = CHANNEL_REGISTER_SHIFT,
   .regmask      = 0x0000FFFFU,
   .dmastream    = STM32_DAC_DAC1_CH2_DMA_STREAM,
 #if STM32_DMA_SUPPORTS_DMAMUX
@@ -178,7 +179,7 @@
 static const dacparams_t dac2_ch2_params = {
   .dac          = DAC2,
   .dataoffset   = CHANNEL_DATA_OFFSET,
-  .regshift     = 16U,
+  .regshift     = CHANNEL_REGISTER_SHIFT,
   .regmask      = 0x0000FFFFU,
   .dmastream    = STM32_DAC_DAC2_CH2_DMA_STREAM,
 #if STM32_DMA_SUPPORTS_DMAMUX
@@ -216,7 +217,7 @@
 static const dacparams_t dac3_ch2_params = {
   .dac          = DAC3,
   .dataoffset   = CHANNEL_DATA_OFFSET,
-  .regshift     = 16U,
+  .regshift     = CHANNEL_REGISTER_SHIFT,
   .regmask      = 0x0000FFFFU,
   .dmastream    = STM32_DAC_DAC3_CH2_DMA_STREAM,
 #if STM32_DMA_SUPPORTS_DMAMUX
@@ -254,7 +255,7 @@
 static const dacparams_t dac4_ch2_params = {
   .dac          = DAC4,
   .dataoffset   = CHANNEL_DATA_OFFSET,
-  .regshift     = 16U,
+  .regshift     = CHANNEL_REGISTER_SHIFT,
   .regmask      = 0x0000FFFFU,
   .dmastream    = STM32_DAC_DAC4_CH2_DMA_STREAM,
 #if STM32_DMA_SUPPORTS_DMAMUX
@@ -375,6 +376,7 @@
      required.*/
   if (dacp->state == DAC_STOP) {
     dacchannel_t channel = 0;
+    uint32_t mcr;
 
     /* Enabling the clock source.*/
 #if STM32_DAC_USE_DAC1_CH1
@@ -381,6 +383,7 @@
     if (&DACD1 == dacp) {
       rccEnableDAC1(true);
     }
+    mcr = STM32_DAC_DAC1_MCR;
 #endif
 
 #if STM32_DAC_USE_DAC1_CH2
@@ -388,6 +391,7 @@
       rccEnableDAC1(true);
       channel = 1;
     }
+    mcr = STM32_DAC_DAC1_MCR;
 #endif
 
 #if STM32_DAC_USE_DAC2_CH1
@@ -394,6 +398,7 @@
     if (&DACD3 == dacp) {
       rccEnableDAC2(true);
     }
+    mcr = STM32_DAC_DAC2_MCR;
 #endif
 
 #if STM32_DAC_USE_DAC2_CH2
@@ -401,6 +406,7 @@
       rccEnableDAC2(true);
       channel = 1;
     }
+    mcr = STM32_DAC_DAC2_MCR;
 #endif
 
 #if STM32_DAC_USE_DAC3_CH1
@@ -407,6 +413,7 @@
     if (&DACD5 == dacp) {
       rccEnableDAC3(true);
     }
+    mcr = STM32_DAC_DAC3_MCR;
 #endif
 
 #if STM32_DAC_USE_DAC3_CH2
@@ -414,6 +421,7 @@
       rccEnableDAC3(true);
       channel = 1;
     }
+    mcr = STM32_DAC_DAC3_MCR;
 #endif
 
 #if STM32_DAC_USE_DAC4_CH1
@@ -420,6 +428,7 @@
     if (&DACD7 == dacp) {
       rccEnableDAC4(true);
     }
+    mcr = STM32_DAC_DAC4_MCR;
 #endif
 
 #if STM32_DAC_USE_DAC4_CH2
@@ -427,10 +436,14 @@
       rccEnableDAC4(true);
       channel = 1;
     }
+    mcr = STM32_DAC_DAC4_MCR;
 #endif
 
+    /* Set MCR on both channels.*/
+    dacp->params->dac->MCR = mcr | (mcr << CHANNEL_REGISTER_SHIFT);
+
     /* Enabling DAC in SW triggering mode initially, initializing data to
-       zero.*/
+       configuration default.*/
 #if STM32_DAC_DUAL_MODE == FALSE
     {
       uint32_t cr;
@@ -445,7 +458,9 @@
     if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
         (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
         (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
-      dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr;
+      dacp->params->dac->CR = DAC_CR_EN2 |
+          (dacp->config->cr << CHANNEL_REGISTER_SHIFT) |
+          DAC_CR_EN1 | dacp->config->cr;
       dac_lld_put_channel(dacp, 1U, dacp->config->init);
     }
     else {
